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05
CY23S09 CY23S05
Low-Cost 3.3V Spread AwareTM Zero Delay Buffer
Features
* 10-MHz to 100-/133-MHz operating range, compatible with CPU and PCI bus frequencies * Zero input-output propagation delay * Multiple low-skew outputs -- Output-output skew less than 250 ps -- Device-device skew less than 700 ps -- One input drives five outputs (CY23S05) -- One input drives nine outputs, grouped as 4 + 4 + 1 (CY23S09) * Less than 200 ps cycle-to-cycle jitter is compatible with Pentium-based systems * Test Mode to bypass PLL (CY23S09 only, see Select Input Decoding table on page 2) * Available in space-saving 16-pin, 150-mil SOIC, 4.4 mm TSSOP, and 150-mil SSOP ( CY23S09) or 8-pin, 150-mil SOIC package (CY23S05) * 3.3V operation, advanced 0.65 CMOS technology * Spread AwareTM up to 100-/133-MHz frequencies, and have higher drive than the -1 devices. All parts have on-chip PLLs that lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The CY23S09 has two banks of four outputs each, which can be controlled by the Select inputs as shown in the Select Input Decoding table on page 2. If all output clocks are not required, Bank B can be three-stated. The select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. The CY23S09 and CY23S05 PLLs enter a power-down mode when there are no rising edges on the REF input. In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 12.0 A of current draw (for commercial temperature devices) and 25.0 A (for industrial temperature devices). The CY23S09 PLL shuts down in one additional case, as shown in the table below. Multiple CY23S09 and CY23S05 devices can accept the same input clock and distribute it. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps. All outputs have less than 200 ps of cycle-to-cycle jitter. The input to output propagation delay on both devices is guaranteed to be less than 350 ps, and the output to output skew is guaranteed to be less than 250 ps. The CY23S05/CY23S09 is available in two different configurations, as shown in the ordering information on page 6. The CY23S05-1/CY23S09-1 is the base part. The CY23S05-1H/ CY23S09-1H is the high-drive version of the -1, and its rise and fall times are much faster than -1.
Functional Description
The CY23S09 is a low-cost 3.3V zero delay buffer designed to distribute high-speed clocks and is available in a 16-pin SOIC package. The CY23S05 is an eight-pin version of the CY23S09. It accepts one reference input, and drives out five low-skew clocks. The -1H versions of each device operate at
Block Diagram
PLL
REF MUX CLKOUT CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 Select Input Decoding S1 CLKB2 CLKB3
Pin Configuration
SOIC/TSSOP/SSOP Top View
REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
CLKOUT
CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1
S2
CY23S09
CLKB4
CY23S09
REF
PLL
CLKOUT CLK1 CLK2 CLK3 CLK4
SOIC Top View
REF CLK2 CLK1 GND
1 2 3 4 8 7 6 5
CLKOUT CLK4 V DD CLK3
CY23S05
CY23S05
Cypress Semiconductor Corporation Document #: 38-07296 Rev. *B
*
3901 North First Street
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San Jose
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CA 95134 * 408-943-2600 Revised December 22, 2002
CY23S05 CY23S09
Select Input Decoding for CY23S09
S2 0 0 1 1 S1 0 1 0 1 CLOCK A1-A4 Three-state Driven Driven Driven CLOCK B1-B4 Three-state Three-state Driven Driven CLKOUT[1] Driven Driven Driven Driven Output Source PLL PLL Reference PLL PLL Shut-down N N Y N
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay between the input and output. Since the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input-output delay. This is shown in the above graph. For applications requiring zero input-output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not used, it must have a capacitive load equal to that on other outputs, for obtaining zero input-output delay. If input to output delay adjustments are required, use the above graph to calculate loading differences between the CLKOUT pin and other outputs. For zero output-output skew, be sure to load all outputs equally. For further information, refer to the application note "CY23S05 and CY23S09 as PCI and SDRAM Buffers."
Spread Aware
Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. Cypress has been one of the pioneers of SSFTG development, and we designed this product so as not to filter off the Spread Spectrum feature of the Reference input, assuming it exists. When a zero delay buffer is not designed to pass the SS feature through, the result is a significant amount of tracking skew which may cause problems in systems requiring synchronization. For more details on Spread Spectrum timing technology, please see the Cypress application note entitled, "EMI Suppression Techniques with Spread Spectrum Frequency Timing Generator (SSFTG) ICs."
Note: 1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
Document #: 38-07296 Rev. *B
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CY23S05 CY23S09
Pin Description for CY23S09
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 REF[2] CLKA1[3] CLKA2[3] VDD GND CLKB1[3] CLKB2[3] S2
[4]
Signal
Description Input reference frequency, 5V-tolerant input Buffered clock output, bank A Buffered clock output, bank A 3.3V supply Ground Buffered clock output, bank B Buffered clock output, bank B Select input, bit 2 Select input, bit 1 Buffered clock output, bank B Buffered clock output, bank B Ground 3.3V supply Buffered clock output, bank A Buffered clock output, bank A Buffered output, internal feedback on this pin
S1[4] CLKB3[3] CLKB4 GND VDD CLKA3[3] CLKA4[3] CLKOUT[3]
[3]
Pin Description for CY23S05
Pin 1 2 3 4 5 6 7 8 REF[2] CLK2[3] CLK1 GND CLK3[3] VDD CLK4[3] CLKOUT[3]
[3]
Signal
Description Input reference frequency, 5V-tolerant input Buffered clock output Buffered clock output Ground Buffered clock output 3.3V supply Buffered clock output Buffered clock output, internal feedback on this pin
Notes: 2. Weak pull-down. 3. Weak pull-down on all outputs. 4. Weak pull-up on these inputs.
Document #: 38-07296 Rev. *B
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CY23S05 CY23S09
Maximum Ratings
Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Input Voltage (Except REF) ............-0.5V to VDD + 0.5V DC Input Voltage REF ............................................. -0.5V to 7V Storage Temperature ................................. -65C to +150C Max. Soldering Temperature (10 sec.) ....................... 260C Junction Temperature................................................. 150C Static Discharge Voltage (per MIL-STD-883, Method 3015) ........................... > 2,000V Unit V C pF pF pF
Operating Conditions for CY23S05SC-XX and CY23S09SC-XX Commercial Temperature Devices [5] Parameter Description Min. Max. VDD TA CL CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance 3.0 0 3.6 70 30 10 7
Electrical Characteristics for CY23S05SC-XX and CY23S09SC-XX Commercial Temperature Devices Parameter VIL VIH IIL IIH VOL VOH IDD (PD mode) IDD Description Input LOW Voltage
[6] [6]
Test Conditions
Min. 2.0
Max. 0.8
Unit V V A A V V
Input HIGH Voltage Input LOW Current
VIN = 0V VIN = VDD IOL = 8 mA (-1) IOH = 12 mA (-1H) IOH = -8 mA (-1) IOL = -12 mA (-1H) REF = 0 MHz Unloaded outputs at 66.67 MHz, SEL inputs at VDD 2.4
50.0 100.0 0.4
Input HIGH Current Output LOW Voltage[7] Output HIGH Voltage[7] Power-down Supply Current Supply Current
12.0 32.0
A mA
Switching Characteristics for CY23S05SC-1 and CY23S09SC-1 Commercial Temperature Devices[8] Parameter t1 Description Output Frequency Duty Cycle[7] = t2 / t1 t3 t4 t5 t6 t7 tJ tLOCK Rise Time
[7]
Test Conditions 30-pF load 10-pF load Measured at 1.4V, Fout = 66.67 MHz Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V
[7]
Min. 10 10 40.0
Typ.
Max. 100 133.33
Unit MHz MHz % ns ns ps ps ps ps ms
50.0
60.0 2.50 2.50 250
Fall Time[7] Output-to-Output Skew Delay, REF Rising Edge to CLKOUT Rising Edge[7] Device-to-Device Skew[7] Cycle-to-Cycle Jitter[7] PLL Lock Time
[7]
All outputs equally loaded Measured at VDD/2 Measured at VDD/2 on the CLKOUT pins of devices Measured at 66.67 MHz, loaded outputs Stable power supply, valid clock presented on REF pin 0 0
350 700 200 1.0
Notes: 5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 6. REF input has a threshold voltage of VDD/2. 7. Parameter is guaranteed by design and characterization. Not 100% tested in production. 8. All parameters specified with loaded outputs.
Document #: 38-07296 Rev. *B
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CY23S05 CY23S09
Switching Characteristics for CY23S05SI-1H and CY23S09SI-1H Industrial Temperature Devices[8] Parameter t1 Description Output Frequency Duty Cycle[7] = t2 / t1 Duty Cycle[7] = t2 / t1 t3 t4 t5 t6 t7 t8 tJ tLOCK Rise Time Fall Time
[7] [7] [7]
Test Conditions 30-pF load 10-pF load Measured at 1.4V, Fout = 66.67 MHz Measured at 1.4V, Fout <50.0 MHz Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V All outputs equally loaded Measured at VDD/2 Measured at VDD/2 on the CLKOUT pins of devices Measured between 0.8V and 2.0V using Test Circuit #2 Measured at 66.67 MHz, loaded outputs Stable power supply, valid clock presented on REF pin
Min. 10 10 40.0 45.0
Typ.
Max. 100 133.33
Unit MHz MHz % % ns ns ps ps ps V/ns
50.0 50.0
60.0 55.0 1.50 1.50 250
Output-to-Output Skew
Delay, REF Rising Edge to CLKOUT Rising Edge[7] Device-to-Device Skew[7] Output Slew Rate[7] Cycle-to-Cycle Jitter[7] PLL Lock Time[7]
0 0 1
350 700
200 1.0
ps ms
Switching Waveforms
Duty Cycle Timing
t1 t2 1.4V 1.4V 1.4V
2309-4
All Outputs Rise/Fall Time
2.0V 0.8V t3 2.0V 0.8V t4
2309-5
3.3V 0V
OUTPUT
Output-Output Skew
OUTPUT
1.4V
OUTPUT t5
1.4V
2309-6
Document #: 38-07296 Rev. *B
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CY23S05 CY23S09
Switching Waveforms (continued)
Input-Output Propagation Delay
INPUT
VDD/2
OUTPUT t6
VDD/2
2309-7
Device-Device Skew
CLKOUT, Device 1
VDD/2
CLKOUT, Device 2 t7
VDD/2
2309-8
Test Circuits Test Circuit # 1 VDD 0.1 F CLK out
OUTPUTS
Test Circuit # 2 VDD 0.1 F
OUTPUTS 1 k
CLOAD VDD 0.1 F
GND GND
10 pF VDD 0.1 F
GND GND 1 k
For parameter t8 (output slew rate) on -1H devices
Ordering Information
Ordering Code CY23S05SC-1 CY23S05SC-1H CY23S09SC-1 CY23S09SC-1H CY23S09ZC-1 CY23S09ZC-1H CY23S09OC-1 CY23S09OC-1H Package Name S8 S8 S16 S16 Z16 Z16 O16 O16 Package Type 8-pin 150-mil SOIC 8-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 4.4mm TSSOP 16-pin 4.4mm TSSOP 16-pin 150-mil SSOP 16-pin 150-mil SSOP Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial
Document #: 38-07296 Rev. *B
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CY23S05 CY23S09
Package Diagram
8-lead (150-Mil) SOIC S8
51-85066-A
16-lead (150-Mil) Molded SOIC S16
51-85068-A
Document #: 38-07296 Rev. *B
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CY23S09 CY23S05
16-lead Thin Shrunk Small Outline Package (4.40-MM Body) Z16
51-85091
16-lead (150-mil) QSOP Q1
51-85053-B
Pentium is a registered trademark of Intel Corporation. Spread Aware is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07296 Rev. *B
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(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY23S05 CY23S09
Document Title: CY23S09/CY23S05 Low-Cost 3.3V Spread AwareTM Zero Delay Buffer Document Number: 38-07296 REV. ** *A *B ECN NO. 111147 111773 122885 Issue Date 11/14/01 02/20/02 12/22/02 Orig. of Change DSG CTK RBI Description of Change Change from spec number 38-01094 to 38-07296 Add 150-mil SSOP option Added power up requirements to Operating Conditions
Document #: 38-07296 Rev. *B
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